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1 typical a pplica t ion descrip t ion 15v, 2.5a synchronous buck-boost dc/dc converter the lt c ? 3112 is a fixed frequency synchronous buck- boost dc/dc converter with an extended input and output range. the unique 4- switch, single inductor architecture provides low noise and seamless operation from input voltages above, below or equal to the output voltage. with an input range of 2.7 v to 15 v, the ltc3112 is well- suited for a wide variety of single or multiple cell battery, backup capacitor or wall adapter source applications. low r ds(on) internal n-channel mosfet switches provide highly efficient operation in applications with higher load current requirements. the ltc3112 features selectable pwm or burst mode operation, an easily synchronized oscillator and output disconnect in shutdown. an output current monitor circuit allows the load current to be controlled or measured. other features include <1 a shutdown current, short circuit protection, soft-start, current limit and thermal shutdown. the ltc3112 is offered in both a 16-pin (4mm 5mm 0.75mm) dfn and 20-pin tssop packages. efficiency at 5v out fea t ures a pplica t ions n regulated output with v in above, below or equal to v out n 2.7v to 15v input voltage range n 2.5v to 14v output voltage range n 2.5a continuous output current: v in 5v, v out = 5v, pwm mode n output current monitor n up to 95% efficiency n 750khz switching frequency, synchronizable between 300khz and 1.5mhz n internal n-channel mosfets n selectable burst mode ? operation, i q = 50a n shutdown current < 1a n overvoltage protection n output disconnect in shutdown n internal soft-start n small, thermally enhanced 16-lead (4mm 5mm 0.75mm) dfn and 20-lead tssop package n 3.3v or 5 v from 1, 2 or 3 li- ion, backup capacitor stack n hand held inventory terminals n rf transmitters n 12v synchronous boost converter n multiple power input systems n led lighting with current regulation n 12 v lead acid battery to 12v l, lt , lt c , lt m , linear technology burst mode, ltspice and the linear logo are registered trademarks and no r sense and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178. v in 4.7h 0.1f 0.1f 680pf 22pf 33k 845k 158k 47pf 47f 1f 10f 10k 42.2k 100pf to adc 1v per amp 5v/2.5a, v in > 5v onoff pwm burst 2.7v to 15v sw1 bst1 v in v cc run gnd pwm/sync sw2 bst2 v out comp i out ovp fb ltc3112 v out 3112 ta01 load current (a) 0.0001 efficiency (%) 100 70 80 50 60 90 30 40 0.01 10.1 3112 ta02 0.001 2.7v in 5.0v in 12v in pwm burst 5v, 750khz wide input voltage range buck-boost regulator ltc3112 3112fc for more information www.linear.com/ltc3112
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in voltage ................................................. C 0. 3 v to 16 v v out voltage .............................................. C 0. 3 v to 15 v sw1 voltage ( note 4) ................... C 0. 3 v to (v in + 0.3 v) sw2 voltage ( note 4) ................ C 0. 3 v to (v out + 0.3 v) v bst 1 voltage ................... ( v sw 1 C 0.3 v) to (v sw 1 + 6v) v bst 2 voltage ................... (v sw 2 C 0.3 v) to (v sw 2 + 6v) (notes 1, 3) 16 15 14 13 12 11 10 9 17 gnd 1 2 3 4 5 6 7 8 pwm/sync v cc bst1 sw1 sw1 bst2 sw2 sw2 comp fb ovp v in v in run i out v out top view dhd16 package 16-lead (5mm 4mm) plastic dfn t jmax =150 c, q ja = 43c/w, q jc = 4c/w exposed pad ( pin 17) is gnd, must be soldered to pcb fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 gnd comp fb ovp v in v in run i out v out gnd gnd pwm/sync v cc bst1 sw1 sw1 bst2 sw2 sw2 gnd 21 gnd t jmax = 150c, q ja = 38c/w, q jc = 4c/w exposed pad ( pin 21) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3112edhd#pbf ltc3112edhd#trpbf 3112 16-lead (5mm 4mm) plastic dfn C40c to 125c ltc3112idhd#pbf ltc3112idhd#trpbf 3112 16-lead (5mm 4mm) plastic dfn C40c to 125c ltc3112hdhd#pbf ltc3112hdhd#trpbf 3112 16-lead (5mm 4mm) plastic dfn C40c to 150c ltc3112mpdhd#pbf ltc3112mpdhd#trpbf 3112 16-lead (5mm 4mm) plastic dfn C55c to 150c ltc3112efe#pbf ltc3112efe#trpbf 3112fe 20-lead plastic tssop C40c to 125c ltc3112ife#pbf ltc3112ife#trpbf 3112fe 20-lead plastic tssop C40c to 125c ltc3112hfe#pbf ltc3112hfe#trpbf 3112fe 20-lead plastic tssop C40c to 150c ltc3112mpfe#pbf ltc3112mpfe#trpbf 3112fe 20-lead plastic tssop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ run voltage ............................................... C 0.3 v to 16 v pwm / sync , v cc , i out voltage .................... C 0. 3 v to 6v fb , c omp , ovp voltage ............................... C 0. 3 v to 6v operating junction temperature range ( notes 2, 6) ............................................................... C55 c to 150 c storage temperature range .................. C 6 5 c to 150 c lead temperature ( soldering , 10 sec ) tssop ....... 30 0 c ltc3112 3112fc for more information www.linear.com/ltc3112
3 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c ( note 2). v in = v out = pwm / sync = run = 5 v unless otherwise noted. e lec t rical c harac t eris t ics parameter conditions min typ max units input operating range 0c to 150c C55c to 0c 2.7 2.85 15 15 v v v in uvlo threshold rising 2.0 2.3 2.7 v v in uvlo hysteresis 300 mv v cc uvlo threshold rising l 2.2 2.35 2.5 v v cc uvlo hysteresis 150 mv output voltage adjust range l 2.5 14 v intv cc clamp voltage v in = 5v or 15v l 3.8 4.2 4.6 v v cc voltage in dropout v in = 2.7v, i vcc = 10ma 2.6 v quiescent current C burst mode operation v fb = 1v, v pwm /sync = 0v 50 75 a quiescent current C shutdown run = v out = v cc = 0v, not including switch leakage 0 1 a feedback voltage = pwm mode operation l 0.778 0.8 0.818 v feedback leakage v fb = 0.8v 0 50 na ovp threshold rising threshold 0.78 0.83 0.88 v ovp hysteresis measured at ovp pin 20 mv ovp leakage ovp = 0.8v 0 100 na nmos switch leakage switch a, b, c, d, v in = v out = 12v 1 10 a nmos switch on resistance switch a 40 m nmos switch on resistance switch b, c 50 m nmos switch on resistance switch d 60 m input current limit l = 4.7h l 4.5 6 8.5 a peak current limit l = 4.7h 7 10 12 a burst current limit l = 4.7h 0.7 1.3 2 a burst zero current threshold l = 4.7h 0.3 a reverse current limit l = 4.7h C0.5 C1 C1.5 a i out accuracy (note 5) sw2 to v out current = 1.5a sw2 to v out current = 1.0a sw2 to v out current = 0.5a 32 20 8 36 24 12 40 28 16 a a a maximum duty cycle buck (switch a on) l 80 87 % boost (switch c on) l 75 82 % minimum duty cycle buck (switch a on) l 0 % boost (switch c on) l 5 12 % frequency pwm /sync = 5v, v in = v out = 12v l 675 750 825 khz sync frequency range (note 7) l 300 1500 khz pwm /sync threshold v cc = 2.7v or 5v l 0.5 0.9 1.5 v run threshold v in = 2.7v or 15v l 0.35 0.75 1.5 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3112 is tested under pulsed load conditions such that t j t a . the ltc3112 e is guaranteed to meet specifications from 0 c to 85 c junction temperature. specifications over the C 40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3112 i is guaranteed to meet specifications over the C 40 c to 125 c operating junction temperature, the ltc3112 h is guaranteed to meet specifications over the C 40 c to 150 c operating junction temperature range and the ltc3112mp is guaranteed and tested to meet specifications over the full C 55 c to 150 c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for temperature greater than 125c . note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. ltc3112 3112fc for more information www.linear.com/ltc3112
4 typical p er f or m ance c harac t eris t ics wide v in to 3.3v out power loss wide v in to 12v out efficiency wide v in to 12v out power loss wide v in to 5v out efficiency wide v in to 5v out power loss wide v in to 3.3v out efficiency t a = 25c, v in = 5.0v, v out = 5.0v unless otherwise specified e lec t rical c harac t eris t ics load current (a) 0.0001 efficiency (%) 100 70 80 50 60 90 30 40 0.01 10.1 3112 g01a 0.001 pwm burst 2.7v in 5.0v in 12v in load current (a) 0.0001 power loss (w) 1 0.01 0.1 0.0001 0.001 0.01 10.1 3112 g01b 0.001 2.7v in loss 5.0v in loss 12v in loss pwm burst load current (a) 0.0001 efficiency (%) 100 70 80 50 60 90 30 40 0.01 10.1 3112 g02a 0.001 pwm burst 2.7v in 5.0v in 12v in load current (a) 0.0001 power loss (w) 1 0.01 0.1 0.0001 0.001 0.01 10.1 3112 g02b 0.001 2.7v in loss 5.0v in loss 12v in loss pwm burst load current (a) 0.0001 efficiency (%) 100 70 80 50 60 90 30 40 0.01 10.1 3112 g03a 0.001 pwm burst 3.6v in 5.0v in 12v in load current (a) 0.0001 power loss (w) 1 0.01 0.1 0.0001 0.001 0.01 10.1 3112 g03b 0.001 3.6v in loss 5.0v in loss 12v in loss pwm burst note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. unction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: voltage transients on the switch pins beyond the dc limit specified in the absolute maximum ratings, are non disruptive to normal operation when using good layout practices, as shown on the demo board or described in the data sheet and application notes. note 5: i out current is tested in a non-switching dc state. in a switching environment i out accuracy may exhibit variation with factors such as switching frequency, load current, input/output voltage, and temperature. see typical performance characteristic curves for predicted variation. note 6: the junction temperature (t , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t = t a (p d ? q q note 7: sync frequency range is tested with a square wave. operation with 100ns minimum high or low times is assured by design. ltc3112 3112fc for more information www.linear.com/ltc3112
5 maximum output current pwm mode maximum output current burst mode operation 12v in to 12v out efficiency vs frequency with 4.7h v in (v) 2 maximum output current (a) 3.2 4.0 4.8 1.6 2.4 0 0.8 4 6 7 8 9 10 11 12 13 14 15 5 3112 g04 3 3.3v out 5.0v out 12v out v in (v) 2 maximum output current (ma) 320 400 480 560 160 240 0 80 4 6 7 8 9 10 11 12 13 14 15 5 3112 g05 3 3.3v out 5.0v out 12v out load current (ma) 0.01 efficiency (%) 70 80 90 100 50 60 30 40 0.1 1 10 3112 g06 500khz 750khz 1000khz 1500khz typical p er f or m ance c harac t eris t ics t a = 25c, v in = 5.0v, v out = 5.0v unless otherwise specified v cc voltage vs v cc current boost mode minimum sw 1 low time vs v cc voltage normalized n-channel mosfet resistance vs v cc 750khz pwm mode no-load input current burst mode no- load input current with v cc from v in or back- fed from v out with optional diode v cc voltage vs v in pwm mode no load v in (v) 2 v in current (ma) 20 25 10 15 0 5 4 6 7 8 9 10 11 12 13 14 15 5 3112 g07 3 v out = 5v v in (v) 3 current from v in (a) 250 300 350 150 200 0 50 100 5 7 9 11 13 15 3112 g08 v out = 5v v cc from v in v cc from v out v in (v) 2 v cc (v) 4.0 4.5 3.0 3.5 2.0 2.5 4 6 7 8 9 10 11 12 13 14 15 5 3112 g09 3 current from v cc (ma) 0 v cc (v) 4.3 4.4 4.1 4.2 3.9 4.0 20 40 60 80 100 120 140 3112 g10 v in = 5v v cc voltage (v) 2.5 minimum sw1 low time (ns) 250 275 200 225 125 175 150 3.5 4 4.5 5 3 3112 g11 v cc (v) 2.5 normalized n-channel mosfet resistance 1.2 1.3 0.9 1.0 1.1 0.7 0.8 3.5 3.75 4 4.25 4.5 4.75 5 2.75 3 3.25 3112 g12 ltc3112 3112fc for more information www.linear.com/ltc3112
6 typical p er f or m ance c harac t eris t ics t a = 25c, v in = 5.0v, v out = 5.0v unless otherwise specified i out pin current vs temperature 1.5a load current i out voltage vs v out current run and pwm /sync threshold voltage vs temperature pwm mode i limit , i peak , i rev vs temperature burst mode operation i peak , i zero vs temperature i out voltage vs v in normalized n-channel mosfet resistance vs temperature feedback pin program voltage vs temperature v cc and v in uvlo vs temperature temperature (c) ?60 normalized n-channel mosfet resistance 1.2 1.3 1.4 0.9 1.0 1.1 0.7 0.8 20 40 60 80 100 120 140 160 ?40 ?20 0 3112 g13 temperature (c) feedback programmed voltage (v) 0.800 0.805 0.810 0.815 0.820 0.825 0.785 0.790 0.795 0.775 0.780 3112 g14 ?60 20 40 60 80 100 120 140 160 ?40 ?20 0 temperature (c) undervoltage lockout (v) 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 1.7 1.8 1.9 1.5 1.6 3112 g15 v in falling v in rising v cc falling v cc rising ?60 20 40 60 80 100 120 140 160 ?40 ?20 0 temperature (c) threshold voltage (v) 0.9 1.0 1.1 1.2 0.6 0.7 0.8 0.4 0.5 3112 g16 run falling run rising pwm/sync falling pwm/sync rising ?60 20 40 60 80 100 120 140 160 ?40 ?20 0 temperature (c) l = 4.7h current (a) 8 10 12 2 4 6 ?2 0 3112 g17 i peak i limit i rev ?60 20 40 60 80 100 120 140 160 ?40 ?20 0 temperature (c) current (a) 1.5 2.0 0.5 1.0 0 3112 g18 i zero i peak l = 4.7h ?60 20 40 60 80 100 120 140 160 ?40 ?20 0 temperature (c) i out pin current (a) 38 39 40 34 35 36 37 32 33 3112 g19 ?60 20 40 60 80 100 120 140 160 ?40 ?20 0 v out current (a) 0 i out voltage (mv) 2500 3000 3500 1000 1500 2000 0 500 1.5 2 2.5 3 3.5 0.5 1 3112 g20 v in = 12v v in = 8v v in = 5v v in = 3v r iout = 42.2k, c iout = 100pf, v out = 5v, 750khz v in (v) 2 3 i out voltage (mv) 1500 2000 2500 500 1000 0 8 97 10 11 12 13 14 15 4 5 6 3112 g21 i out = 2a i out = 1.5a i out = 1a i out = 500ma r iout = 42.2k, c iout = 100pf, v out = 5v, 750khz ltc3112 3112fc for more information www.linear.com/ltc3112
7 typical p er f or m ance c harac t eris t ics t a = 25c, v in = 5.0v, v out = 5.0v unless otherwise specified i out voltage vs v out i out voltage vs v in and switching frequency 3.3v out die temperature rise vs continuous load current 4 layer demo board at 25c v out (v) 2 3 i out voltage (mv) 1500 2000 2500 500 1000 0 8 97 10 11 12 13 14 4 5 6 3112 g22 i out = 2a i out = 1.5a i out = 1a i out = 500ma r iout = 42.2k, c iout = 100pf, v in = 7.5v, 750khz v in (v) 2 3 i out voltage (mv) 1500 2000 2500 500 1000 0 8 97 10 11 12 13 14 15 4 5 6 3112 g23 2a, 1500khz 2a, 750khz 2a, 300khz 1a, 1500khz 1a, 750khz 1a, 300khz r iout = 42.2k, c iout = 100pf, v out = 5v, 750khz load current (a) 0 temperature rise (c) 30 40 50 60 10 20 0 0.5 1 1.5 4 2 2.5 3 3.5 3112 g24 v in = 2.7v v in = 5v v in = 12v 5v out die temperature rise vs continuous load current 4 layer demo board at 25c 12v out die temperature rise vs continuous load current 4 layer demo board at 25c load current (a) 0 temperature rise (c) 30 40 50 60 10 20 0 0.5 1 1.5 4 2 2.5 3 3.5 3112 g25 v in = 2.7v v in = 5v v in = 12v load current (a) 0 temperature rise (c) 30 40 50 60 10 20 0 0.5 1 1.5 4 2 2.5 3 3.5 3112 g26 v in = 5v v in = 12v 3112 g27 v out 200mv/div 500s/div front page application inductor current 1a/div 3112 g28 v out 200mv/div 500s/div front page application inductor current 1a/div 3112 g29 v out 200mv/div inductor current 1a/div 500s/div front page application 3v in to 5v out 0.1a to 0.6a load step 5v in to 5v out 0.1a to 1.0a load step 12v in to 5v out 0.1a to 1.0a load step 5v in to 5.0v out burst to pwm waveforms, 3112 g30 v out 500mv/div inductor current 500ma/div pwm/sync 5v/div 100s/div 100ma load c out = 47f ltc3112 3112fc for more information www.linear.com/ltc3112
8 typical p er f or m ance c harac t eris t ics t a = 25c, v in = 5.0v, v out = 5.0v unless otherwise specified 3112 g31 v out 100mv/div inductor current 500ma/div 20s/div 100ma load c out = 47f 3112 g32 v out 50mv/div inductor current 1a/div 1s/div 12.0v in to 5.0v out 1a load c out = 47f 3112 g33 v in 2v/div v out 2v/div inductor current 1a/div 1ms/div i l 1a/div 3112 g34 pwm/sync 5v/div inductor current 500ma/div 10s/div 3112 g36 sw2 5v/div sw1 5v/div inductor current 1a/div 500ns/div i load = 2a 750khz 3112 g37 v out 2v/div v out shorted inductor current 5a/div 200s/div v in = 5v 3112 g38 v cc 5v/div v out 2v/div inductor current 1a/div 500s/div v cc shorted v out soft-starts 12v in to 5v out burst mode operation waveforms pwm v out ripple 7.5v in to 5.0v out soft-start waveforms 1500khz sync signal capture and release 12v in to 5.0v out sw1 and sw2 waveforms v out short circuit response v cc short circuit recovery ltc3112 3112fc for more information www.linear.com/ltc3112
9 p in func t ions comp (pin 1/pin 2): error amp output. an r-c network connected from this pin to fb sets the loop compensation for the voltage converter. fb (pin 2/pin 3): feedback voltage input. connect v out resistor divider tap to this pin. the output voltage can be adjusted from 2.5v to 14v by the following equation: v out = 0.8v ? 1 + r1 r2 ? ? ? ? ? ? where r 1 is the resistor between v out and fb and r2 is the resistor between fb and gnd. ovp (pin 3/pin 4): overvoltage protection input. the common point of a resistor divider between v out and gnd can also be used to program the overvoltage protection to a lower voltage by the following equation: v ovp = 0.83v ? 1 + r3 r4 ? ? ? ? ? ? where r3 is the resistor between v out and ovp and r4 is the resistor between ovp and gnd. v in (pins 4, 5/pins 5, 6): input supply voltage. this pin should be bypassed to the ground plane with at least 10f of low esr, low esl ceramic capacitance. place this capacitor as close to the pin as possible and have as short a return path to the ground plane as possible. run (pin 6/pin 7): shutdown control input. operation will be disabled when the voltage is forced below 0.75v (typical) and less than 1 a of quiescent current will be consumed. i out (pin 7/pin 8): a current approximately 24 a/a of the d switch output current is sourced from this pin. an r-c circuit can be used to control the average output current or provide an analog output current monitor ( see applications information section). v out (pin 8/pin 9): regulated output voltage. this pin should be connected to a low esr ceramic capacitor of at least 47 f. the capacitor should be placed as close to the pin as possible and have a short return to the ground plane. sw2 (pins 9, 10/pins 12, 13): internal switches c and d and the external inductor are connected here. bst 2 ( pin 11/pin 14): boosted floating driver supply for d-switch driver. connect a 0.1 f capacitor from this pin to sw2. sw1 (pins 12, 13/pins 15, 16): internal switches a and b and the external inductor are connected here. bst1 (pin 14/pin 17): boosted floating driver supply for a-switch driver. connect a 0.1 f capacitor from this pin to sw1. v cc (pin 15/pin 18): external capacitor connection for the regulated v cc supply. this supply is used to operate internal circuitry and switch drivers. v cc will track v in up to 4.2 v, but will maintain this voltage when v in > 4.2 v. connect a 1f ceramic capacitor from this pin to gnd. pwm /sync (pin 16/pin 19): burst mode control and syn - chronization input. a dc voltage <0.5 v commands burst mode operation, >1.5 v commands 750khz fixed frequency mode. a digital pulse train between 300 khz and 1500khz applied to this pin will override the internal oscillator and set the operating frequency. the pulse train should have minimum high or low times greater than 100ns (note 7). note the ltc3112 has reduced power capability when operating in burst mode operation. refer to the operation section of this data sheet for details. gnd ( exposed pad pin 17/pins 1, 10, 11, 20, exposed pad pin 21): ground. small-signal and power ground for the ic. the exposed pad must be soldered to the pcb and electrically connected to ground through the shortest and lowest impedance connection possible. the bulk of the heat flow is through this pad, so printed circuit board design has an impact on the thermal performance of the ic. see pcb layout and thermal considerations sections for more details. (dfn/tssop) ltc3112 3112fc for more information www.linear.com/ltc3112
10 b lock diagra m v cc v cc v cc v cc v cc v cc v cc 2.7v to 15v v in 5v v out bst1 4.7h bst2 gnd fb comp pwm/ sync i out sw1 sw2 v in v out 24a/a adrv bdrv cdrv ddrv drivers + ? + ? + ? + ? 300ma 10a 6a logic + ? reverse i lim ?1a + + ? ? + onoff 2.3v a b d c + ? + ? adrv bdrv ddrv cdrv 0.9v burst mode operation pll 750khz oscillator 0.8v soft-start ramp i zero i peak i limit gnd run ovp v cc v cc v in overvoltage protection 4.2v regulator /clamp reference 1.2v uvlo ltc3112 3112fc for more information www.linear.com/ltc3112
11 o pera t ion introduction the ltc3112 is an extended input and output range, high current synchronous buck-boost dc/dc converter optimized for a variety of demanding applications. the ltc3112 utilizes a proprietary switching algorithm, which allows its output voltage to be regulated above, below or equal to the input voltage . the error amplifier output on comp determines the output duty cycle of the switches. the low r ds(on) , low gate charge synchronous switches provide high efficiency pulse width modulation control. high efficiency is achieved at light loads when burst mode operation is commanded. low noise fixed frequency operation oscillator, phase-locked loop an internal oscillator circuit sets the normal frequency of operation to 750khz. a pulse train applied to the pwm / sync pin allows the operating frequency to be programmed between 300khz to 1.5mhz via an internal phase- locked loop circuit. the pulse train must have a minimum high or low state of at least 100ns to guarantee operation ( note 7). error amplifier the error amplifier is a high gain voltage mode ampli - fier. the loop compensation components are configured around the amplifier ( from fb to comp and v out to fb) to obtain stability of the converter and rapid response to load transients . refer to the applications information section of this data sheet under closing the feedback loop for information on selecting compensation type and components. current limit operation the buck-boost converter has two current limit circuits . the primary current limit is an average current limit circuit which sources current into the feedback divider network proportional to the extent that switch a current exceeds 6a typical. due to the high gain of the feedback loop, the injected current forces the error amplifier output to decrease until the average current through switch a decreases ap - proximately to the current limit value. the average cur- rent limit utilizes the error amplifier in an active state and thereby provides a smooth recovery with little overshoot once the current limit fault condition is removed. since the current limit is based on the average current through switch a, the peak inductor current in current limit will have a dependency on the duty cycle ( i.e. on the input and output voltages) in the overcurrent condition. for this current limit feature to be most effective, the thevenin resistance from the fb to ground should exceed 100k. the speed of the average current limit circuit is limited by the dynamics of the error amplifier. on a hard output short, it would be possible for the inductor current to increase substantially beyond current limit before the average cur - rent limit circuit would react. for this reason, there is a second current limit circuit which turns off switch a if the current ever exceeds approximately 160% of the average current limit value. this provides additional protection in the case of an instantaneous hard output short. should the output become shorted, the average current limit is reduced to approximately one half of the normal operating current limit. reverse current limit during fixed frequency operation, a reverse current com - parator on switch d monitors the current entering the v out pin. when this reverse current exceeds 1a (typical) switch d will be turned off for the remainder of the switch- ing cycle . this feature protects the buck-boost converter from excessive reverse current if the buck-boost output is above the regulation voltage. internal soft-start the ltc3112 buck-boost converter has an independent internal soft-start circuit with a nominal duration of 2ms. the converter remains in regulation during soft-start and will therefore respond to output load transients which occur during this time . in addition, the output voltage rise time has minimal dependency on the size of the output capacitor or load current during start-up. ltc3112 3112fc for more information www.linear.com/ltc3112
12 o pera t ion thermal considerations for the ltc3112 to provide maximum output power, it is imperative that a good thermal path be provided to dis - sipate the heat generated within the package. this can be accomplished by taking advantage of the large thermal pad on the underside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct the heat away from the ic and into a copper plane with as much area as possible. the efficiency and maximum output current capability of the ltc3112 will be reduced if the converter is required to continuously deliver large amounts of power or operate at high ambient temperatures. the amount of output current derating is dependent upon factors such as board ground plane or heat sink area, ambient operating temperature, and the input/output voltages of the application. a poor thermal design can cause excessive heating, resulting in impaired performance or reliability. the temperature rise curves given in the typical perfor - mance characteristics section can be used as a general guide to predict junction temperature rise from ambient. these curves were generated by mounting the ltc3112 to the 4- layer fr4 demo board printed circuit board layout shown in figure 3. the curves were taken with the board at room temperature, elevated ambient temperatures will result in greater thermal rise rates due to increased initial r ds(on) of the n-channel mosfets . the die temperature of the ltc3112 should be kept below the maximum junc- tion rating of 150c. in the event that the junction temperature gets too high (approximately 150o c), the current limit will be linearly decreased from its typical value. if the junction temperature continues to rise and exceeds approximately 170 c the ltc3112 will be disabled. all power devices are turned off and all switch nodes put to a high impedance state. the soft-start circuit for the converter is reset during thermal shutdown to provide a smooth recovery once the overtem - perature condition is eliminated. when the die temperature drops to approximately 160c the ltc3112 will re-start. undervoltage lockouts the ltc3112 buck-boost converter is disabled and all power devices are turned off until the v cc supply reaches 2.35v ( typical). the soft-start circuit is reset during under- voltage lockout to provide a smooth restart once the input voltage rises above the undervoltage lockout threshold. a second uvlo circuit disables all power devices if v in is below 2.3 v rising, 2.0 v falling ( typical). this can provide a lower v in operating range in applications where v cc is powered from an alternate source or v out after start-up. inductor damping when the ltc3112 is disabled (run = 0 v) or sleeping during burst mode operation ( pwm /sync = 0 v), active circuits damp the inductor voltage through a 250 ( typi - cal) impedance from sw1 and sw2 to gnd to minimize ringing and reduce emi. pwm mode operation when the pwm / sync pin is held high, the ltc3112 buck- boost converter operates in a fixed frequency pulse width modulation ( pwm ) mode using voltage mode control. full output current capability is only available in pwm mode. a proprietary switching algorithm allows the converter to tran - sition between buck, buck- boost, and boost modes without discontinuity in inductor current. the switch topology for the buck- boost converter is shown in figure 1. v in v out a l b d c 3112 f01 figure 1. buck-boost switch topology when the input voltage is significantly greater than the output voltage, the buck-boost converter operates in buck mode. switch d turns on at maximum duty cycle and switch c turns on just long enough to refresh the voltage on the bst2 capacitor used to drive switch d. switches a and b ltc3112 3112fc for more information www.linear.com/ltc3112
13 are pulse width modulated to produce the required duty cycle to support the output regulation voltage. as the input voltage nears the output voltage, switches a and d are on for a greater portion of the switching period, providing a direct current path from v in to v out . switches b and c are turned on only enough to ensure proper regulation and/or provide charging of the bst1 and bst2 capacitors. the internal control circuitry will determine the proper duty cycle in all modes of operation, which will vary with load current. as the input voltage drops well below the output voltage, the converter operates solely in boost mode. switch a turns on at maximum duty cycle and switch b turns on just long enough to refresh the voltage on the bst1 capacitor used to drive a . switches c and d are pulse width modulated to produce the required duty cycle to regulate the output voltage. this switching algorithm provides a seamless transition between operating modes and eliminates discontinuities in average inductor current, inductor current ripple, and loop transfer function throughout the operational modes. these advantages result in increased efficiency and stab - ility in comparison to the traditional 4- switch buck-boost converter. powering v cc from an external source the ltc3112s v cc regulator can be powered or back-fed from an external source up to 5.5 v. advantages of back- feeding v cc from a voltage above 4.2 v include higher efficiency and improved maximum duty cycle at lower input voltages. these advantages are shown in the typical performance characteristics curves mosfet resistance vs v cc and minimum sw1 low times. for 5v out ap- plications, v cc can be easily powered from v out using an external low current schottky diode as shown in several applications circuits in the typical applications section. back-feeding v cc also improves a light load pwm mode output voltage ripple that occurs when the inductor passes through zero current. back - feeding v cc reduces the switch pin anti-cross conduction times, minimizing the v out ripple during this light-load condition. one disadvantage of powering v cc from v out is that no-load quiescent current increases at low v in in burst mode operation as o pera t ion shown in the typical performance characteristics curves (compared to v cc powered from v in ). considerations for boost applications in boost mode, the maximum output current that can be supported at higher v out /v in ratios is reduced. this ef- fect is illustrated in the maximum output current pw m mode curves in the typical performance characteristics section. for example at 12v out , the ltc3112 needs v in > 4v to support 1 a. as described previously, powering v cc from a 5 v source ( if available) can improve output current capabilities at low input voltages. at even lower input voltages (below 3.6 v for 12v out ), the ltc3112 can run into duty cycle limitations. this occurs since sw1 and sw2 maximum duty cycles are multiplied, giving an approximate 70% maximum duty cycle at the nominal 750khz switching frequency. reducing the switch - ing frequency with the pwm /sync pin will increase the maximum duty cycle, allowing a higher boost ratio to be achieved. do not attempt operating the ltc3112 beyond the duty cycle limitations described as this may result in unstable operation. burst mode operation when the pwm /sync pin is held low, the buck-boost converter operates utilizing a variable frequency switch - ing algorithm designed to improve efficiency at light load and reduce the standby current at zero load. in burst mode operation, the inductor is charged with fixed peak amplitude current pulses and as a result only a fraction of the maximum output current can be delivered when in burst mode operation. these current pulses are repeated as often as necessary to maintain the output regulation voltage. the maximum output current, i max , which can be supplied in burst mode operation is dependent upon the input and output voltage as approximated by the following formula: i max = 0.5 ? v in v in + v out (a) if the buck-boost load exceeds the maximum burst mode current capability, the output rail will lose regulation. in ltc3112 3112fc for more information www.linear.com/ltc3112
14 the basic ltc3112 application circuit is shown on the front page of this data sheet. the external component selection is dependent upon the required performance of the ic in each particular application given trade-offs such as pcb area, output voltages, output currents, ripple voltages and efficiency. this section of the data sheet provides some basic guidelines and considerations to aid in the selection of external components and the design of the application circuit. v out and ovp programming the buck - boost output voltage is set with an external resis - tor divider connected to the fb pin as shown in figure 2. the resistor divider values determine the buck- boost output voltage according to the following formula: a pplica t ions i n f or m a t ion v out 2.5v < v out < 14v r3 r4 r1 r2 c1 ltc3112 gnd ovp fb 3112 f02 figure 2. setting the output voltage v out = 0.8v ? 1 + r1 r2 ? ? ? ? ? ? if accurate overvoltage protection is required, a second resistor divider ( r3 and r4) may be connected to the ovp pin to program the overvoltage protection threshold where the ltc3112 will stop switching. v ovp = 0.83v ? 1 + r3 r4 ? ? ? ? ? ? a small capacitor, c1, in parallel with r4 may be needed to provide filtering to prevent nuisance trips during a load step. a soft-start cycle will be initiated if an overvoltage event occurs. inductor selection to achieve high efficiency, a low esr inductor should be utilized for the buck-boost converter. in addition, the buck- boost inductor must have a saturation current rating that is greater than the worst case average inductor current plus half the ripple current. the peak-to-peak inductor current ripple for buck or boost mode operation can be calculated from the following formulas: ?i l,p ? p, buck = v out f ? l v in ? v out v in ? ? ? ? ? ? a ?i l,p ? p, boost = v in f ? l v out ? v in v out ? ? ? ? ? ? a o pera t ion burst mode operation, the error amplifier is configured for low power operation and used to hold the compensation pin comp, to reduce transients that may occur during transitions from and to burst and pwm mode. o utput c urrent m onitor the ltc3112 includes a circuit that sources an approximate 24a/a current replica of the v out ( or swd) current. this current is typically passed through a resistor from i out to gnd and filtered to produce a dc voltage proportional to average load current. this voltage can be monitored by an a/d converter to track load conditions. the i out pin voltage can also control ltc3112s feedback loop to regulate i out current instead of v out voltage. the accuracy of the i out replica depends on factors such as duty cycle, v in and v out voltages, operating frequency etc. the i out pins dc voltage must be less than v cc - 1 v to provide an accurate representation of output current. ltc3112 3112fc for more information www.linear.com/ltc3112
15 a pplica t ions i n f or m a t ion where f is the switching frequency in hz and l is the inductor value in henries. in addition to affecting output current ripple, the size of the inductor can also impact the stability of the feedback loop. in boost mode, the converter transfer function has a right half plane zero at a frequency that is inversely proportional to the value of the inductor. as a result, a large inductor can move this zero to a frequency that is low enough to degrade the phase margin of the feedback loop. it is rec - ommended that the inductor value be chosen less than 15h if the converter is to be used in the boost region. for 750 khz operation, a 4.7 h inductor is recommended for 5v out and a 10h inductor for 12v out . the inductor dc resistance can impact the efficiency of the buck-boost converter as well as the maximum output current capability at low input voltage. in buck mode, the output current is limited only by the inductor current reaching the current limit value. however, in boost mode, especially at large step-up ratios, the output current capa - bility can also be limited by the total resistive losses in the power stage. these include switch resistances, inductor resistance, and pcb trace resistance. use of an inductor with high dc resistance can degrade the output current capability from that shown in the graph in the typical performance characteristics section of this data sheet. different inductor core materials and styles have an impact on the size and price of an inductor at any given current rating. shielded construction is generally preferred as it minimizes the chances of interference with other circuitry. the choice of inductor style depends upon the price, sizing , and emi requirements of a particular application. table 1 provides a small sampling of inductors that are well suited to many ltc3112 buck-boost converter applications. all inductor specifications are listed at an inductance value of 4.7 h for comparison purposes but other values within these inductor families are generally well suited to this application. within each family ( i.e. at a fixed size), the dc resistance generally increases and the maximum current generally decreases with increased inductance. table 1. representative buck-boost surface mount inductors part number value (h) dcr (m) max i (a) size (mm) w l h coilcraft xpl7030-472ml 4.7 40.1 6.8 7 7 3 coilcraft mss1048-472nlb 4.7 12.3 6.46 10 10 4.8 wrth 744 311 470 4.7 24 6 7 6.9 3.8 cooper bussmann hc8-4r 5- r 4.5 18.6 7.7 10.9 10.4 4 output capacitor selection a low-esr output capacitor should be utilized at the buck- boost converter output in order to minimize output volt - age ripple. multilayer ceramic capacitors are an excellent choice as they have low esr and are available in small footprints. the capacitor should be chosen large enough to reduce the output voltage ripple to acceptable levels. the minimum output capacitor needed for a given output voltage ripple ( neglecting esr and esl) can be calculated by the following formulas: c out = 1 ? v p ? p, buck 8 ? l ? f 2 ? v in ? v out ( ) v out v in c out = i load v out ? v in ( ) ? v p ? p, boost v out ? f where f is the frequency in mhz, c out is the capacitance in f, l is the inductance in h, and i load is the output current in amps. given that the output current is discontinuous in boost mode, the ripple in this mode will generally be much larger than the magnitude of the ripple in buck mode. for most applications a 47 f or greater output capacitor is recommended. input capacitor selection it is recommended that a low esr ceramic capacitor with a value of at least 10 f be located as close to the v in and gnd pins as possible. in addition, the return trace from each pin to the ground plane should be made as short as possible. for instances where the input source, such as a bench supply, is far away from the converter, a bulk capacitor of 100 f or greater is suggested to provide a low ripple input voltage especially in buck mode. ltc3112 3112fc for more information www.linear.com/ltc3112
16 capacitor vendor information both the input bypass capacitors and output capacitors used with the ltc3112 must be low esr and designed to handle the large ac currents generated by switching converters. this is important to maintain proper functioning of the ic and to reduce ripple on both the input and output. many modern low voltage ceramic capacitors experience significant loss in capacitance from their rated value with increased dc bias voltages. for example, it is not uncom - mon for a small surface mount ceramic capacitor to lose 50% or more of its rated capacitance when operated near its rated voltage. as a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a higher voltage rating then required in order to actually realize the intended capacitance at the full operating voltage. for details, consult the capacitor vendor s curve of capacitance versus dc bias voltage. the capacitors listed in table 2 provide a sampling of small surface mount ceramic capacitors that are well suited to ltc3112 application circuits. all listed capacitors are either x5r or x7r dielectric in order to ensure that capacitance loss overtemperature is minimized. table 2. representative bypass and output capacitors part number value (f) volt age (v) size (mm) l w h avx ld103d226mab2a 22 25 3.2 2.5 2.79 kemet c1210c476m4 pac 7025 47 16 3.2 2.5 2.5 murata grm32er61e226ke15l 22 25 3.6 2.5 2.5 taiyo yuden emk325bj476mm-t 47 16 3.2 2.5 2.5 tdk c5750x5ric476m 47 16 5.7 5 2.3 pcb layout considerations the ltc3112 switches large currents at high frequencies. special attention should be paid to the pcb layout to ensure a stable, noise - free and efficient application circuit. figure 3 presents a representative 4- layer pcb layout to outline some of the primary considerations. a few key guidelines are outlined below: 1. a 4 - layer board is highly recommended for the ltc3112 to ensure stable performance over the full operating voltage and current range. a dedicated/solid ground a pplica t ions i n f or m a t ion plane should be placed directly under the v in , v out , sw1 and sw2 traces to provide a mirror plane to minimize noise loops from high di/dt and dv/dt edges (see figure 3, 2nd layer). 2. all circulating high current paths should be kept as short as possible. capacitor ground connections should via down to the ground plane in the shortest route possible. the bypass capacitors on v in should be placed as close to the ic as possible and should have the shortest possible paths to ground ( see figure 3, top layer). 3. the exposed pad is the power ground connection for the ltc3112. multiple vias should connect the back pad directly to the ground plane. in addition maximi - zation of the metallization connected to the back pad will improve the thermal environment and improve the power handling capabilities of the ic. 4. the high current components and their connections should all be placed over a complete ground plane to minimize loop cross-sectional areas. this minimizes emi and reduces inductive drops. 5. connections to all of the high current components should be made as wide as possible to reduce the series resistance. this will improve efficiency and maximize the output current capability of the buck- boost converter. 6. to prevent large circulating currents from disrupting the output voltage sensing, the ground for each resistor divider should be returned to the ground plane using a via placed close to the ic and away from the power connections. 7. keep the connection from the resistor dividers to the feedback pins fb as short as possible and away from the switch pin connections. 8. crossover connections should be made on inner cop - per layers if available. if it is necessary to place these on the ground plane, make the trace on the ground plane as short as possible to minimize the disruption to the ground plane (see figure 3, 3rd layer). ltc3112 3112fc for more information www.linear.com/ltc3112
17 a pplica t ions i n f or m a t ion cin cout l figure 3. example pcb layout top layer 2nd layer 3rd layer bottom layer ( top view) ltc3112 3112fc for more information www.linear.com/ltc3112
18 a pplica t ions i n f or m a t ion buck mode small signal model the ltc3112 uses a voltage mode control loop to main- tain regulation of the output voltage. an externally com- pensated error amplifier drives the comp pin to generate the appropriate duty cycle of the power switches. use of an external compensation network provides the flexibility for optimization of closed loop performance over the wide variety of output voltages, switching frequencies, and external component values supported by the ltc3112. the small signal transfer function of the buck-boost con- verter is different in the buck and boost modes of opera - tion and care must be taken to ensure stability in both operating regions. when stepping down from a higher input voltage to a lower output voltage, the converter will operate in buck mode and the small signal transfer function from the error amplifier output, v comp , to the converter output voltage is given by the following equation . v o v comp buck mode = g buck 1 + s 2 f z ? ? ? ? ? ? 1 + s 2 f o q + s 2 f o ? ? ? ? ? ? ? ? 2 the gain term, g buck , is comprised of two different com- ponents: the gain of the pulse width modulator and the gain of the power stage as given by the following expressions where v in is the input voltage to the converter in volts, f is the switching frequency in hz, r is the load resistance in ohms, and t low is the switch pin minimum low time. a curve showing the switch pin minimum low time can be found in the typical performance characteristics sec - tion of this data sheet. the parameter r s represents the average series resistance of the power stage and can be approximated as twice the average power switch resistance plus the dc resistance of the inductor. g buck = g pwm g power g pwm = 2 1C t low f ( ) g power = v in r 1C t low f ( ) r + r s ( ) the buck mode gain is well approximated by the follow- ing equation. g buck = 2 ? v in ? r r + r s ? 2 ? v in the buck mode transfer function has a single zero which is generated by the esr of the output capacitor. the zero frequency, f z , is given by the following expression where r c and c o are the esr ( in ohms) and value ( in farads) of the output filter capacitor respectively. f z = 1 2 r c c o in most applications, an output capacitor with a very low esr is utilized in order to reduce the output voltage rip- ple to acceptable levels. such low values of capacitor esr result in a very high frequency zero and as a result the zero is commonly too high in frequency to significantly impact compensation of the feedback loop. the denominator of the buck mode transfer function ex- hibits a pair of resonant poles generated by the lc filtering of the power stage. the resonant frequency of the power stage, f o , is given by the following expression where l is the value of the inductor in henries. f o = 1 2 r + r s lc o r + r c ( ) ? 1 2 1 lc o the quality factor, q, has a significant impact on com- pensation of the voltage loop since a higher q factor produces a sharper loss of phase near the resonant frequency. the quality factor is inversely related to the amount of damping in the power stage and is substantially influenced by the average series resistance of the power stage, r s . lower values of r s will increase the q and result in a sharper loss of phase near the resonant frequency and will require more phase boost or lower bandwidth to maintain an adequate phase margin. q = lc o r + r c ( ) r + r s ( ) rr c c o + l + c o r s r + r c ( ) ? lc o l r + c o r s ltc3112 3112fc for more information www.linear.com/ltc3112
19 a pplica t ions i n f or m a t ion boost mode small signal model when stepping up from a lower input voltage to a higher output voltage, the buck-boost converter will operate in boost mode where the small signal transfer function from control voltage, v comp , to the output voltage is given by the following expression. v o v comp boost mode = g boost 1 + s 2 f z ? ? ? ? ? ? 1C s 2 f rhpz ? ? ? ? ? ? 1 + s 2 f o q + s 2 f o ? ? ? ? ? ? 2 in boost mode operation, the transfer function is character - ized by a pair of resonant poles and a zero generated by the esr of the output capacitor as in buck mode. however, in addition there is a right half plane zero which generates increasing gain and decreasing phase at higher frequen - cies. as a result, the crossover frequency in boost mode operation generally must be set lower than in buck mode in order to maintain sufficient phase margin. the boost mode gain, g boost , is comprised of two com- ponents: the pulse width modulator and the power stage. the gain of the power stage in boost mode is given by the following equation. g power ? v out 2 1C t low f ( ) v in by combining the individual terms, the total gain in boost mode can be reduced to the following expression. notice that unlike in buck mode, the gain in boost mode is a function of both the input and output voltage. g boost ? 2 ? v out 2 v in in boost mode operation, the frequency of the right half plane zero, f z , is given by the following expression. the frequency of the right half plane zero decreases at higher loads and with larger inductors. f rhpz = r 1C t low f ( ) 2 v in 2 2 l v out 2 in boost mode, the resonant frequency of the power stage has a dependence on the input and output voltage as shown by the following equation. f o = 1 2 r s + rv in 2 v out 2 lc o r + r c ( ) ? 1 2 ? v in v out 1 lc finally, the magnitude of the quality factor of the power stage in boost mode operation is given by the following expression. q = lc o r r s + rv in 2 v out 2 ? ? ? ? ? ? l + c o r s r compensation of the voltage loop the small signal models of the ltc3112 reveal that the transfer function from the error amplifier output, v comp , to the output voltage is characterized by a set of resonant poles and a possible zero generated by the esr of the output capacitor as shown in the bode plot of figure 4. in boost mode operation, there is an additional right half plane zero that produces phase lag and increasing gain at higher freq uencies . typically, the compensation network is designed to ensure that the loop crossover frequency is low enough that the phase loss from the right half plane zero is minimized. the low frequency gain in buck mode is a constant, but varies with both v in and v out in boost mode. figure 4. buck-boost converter bode plot gain phase boost mode buck mode ?20db/dec ?40db/dec f o f 3112 f06 f rhpz 0 ?90 ?180 ?270 ltc3112 3112fc for more information www.linear.com/ltc3112
20 for charging, led lighting, or other applications that do not require an optimized output voltage transient re-sponse, a simple type i compensation network as shown in figure 5 can be used to stabilize the voltage loop. to ensure suf - ficient phase margin, the gain of the error am-plifier must be low enough that the resultant crossover frequency of the control loop is well below the resonant frequency. + ? c1 gnd ltc3112 v comp 3112 f05 fb v out r bot r top 0.8v in most applications, the low bandwidth of the type i com- pensated lo op wi ll not provide sufficient transient response performance. to obtain a wider bandwidth feedback loop, optimize the transient response, and minimize the size of the output capacitor, a type iii com-pensation network as shown in figure 6 is required. figure 5. error amplifier with type i compensation c fb r fb gnd ltc3112 v comp 3112 f06 fb v out r bot r top r ff c ff 0.8v c pole + ? figure 6. error amplifier with type iii compensation a bode plot of the typical type iii compensation network is shown in figure 7. the type iii compensation network provides a pole near the origin which produces a very high loop gain at dc to minimize any steady state error in the regulation voltage. tw o zeros located at f zero1 and f zero2 provide sufficient phase boost to allow the loop crossover frequency to be set above the resonant frequency, f o , of the power stage. the type iii compensation network also introduces a second and third pole. the second pole, at frequency f pole2 , reduces the error amplifier gain to a zero slope to prevent the loop crossover from extending too high in frequency. the third pole at frequency f pole3 provides attenuation of high frequency switching noise. a pplica t ions i n f or m a t ion f zero1 phase 90 ?90 0 gain ?20db/dec ?20db/dec f zero2 3112 f07 f f pole2 f pole3 figure 7. type iii compensation bode plot. the transfer function of the compensated type iii error amplifier from the input of the resistor divider to the output of the error amplifier, v comp , is: v comp (s) v out (s) = g ea 1 + s 2 f zero1 ? ? ? ? ? ? 1 + s 2 f zero2 ? ? ? ? ? ? s 1 + s 2 f pole1 ? ? ? ? ? ? 1 + s 2 f pole2 ? ? ? ? ? ? the error amplifier gain is given by the following equation. the simpler approximate value is sufficiently accurate in most cases since c fb is typically much larger in value than c pole . g ea = 1 r top c fb + c pole ( ) ? 1 r top c fb the pole and zero frequencies of the type iii compensation network can be calculated from the following equations where all frequencies are in hz, resistances are in ohms, and capacitances are in farads. ltc3112 3112fc for more information www.linear.com/ltc3112
21 f zero1 = 1 2 r fb c fb f zero2 = 1 2 r top + r ff ( ) c ff ? 1 2 r top c ff f pole2 = c fb + c pole 2 c fb c pole r fb ? 1 2 c pole r fb f pole3 = 1 2 c ff r ff in most applications the compensation network is de- signed so that the loop crossover frequency is above the resonant frequency of the power stage, but sufficiently below the boost mode right half plane zero to minimize the additional phase loss. once the crossover frequency is decided upon, the phase boost provided by the com- pensation network is centered at that point in order to maximize the phase margin. a larger separation in frequency between the zeros and higher order poles will provide a higher peak phase boost but may also increase the gain of the error amplifier which can push out the loop crossover to a higher frequency. the q of the power stage can have a significant influence on the design of the compensation network because it determines how rapidly the 180 of phase loss in the power stage occurs. for very low values of series resistance, r s , the q will be higher and the phase loss will occur sharply. in such cases, the phase of the power stage will fall rapidly to C180 above the resonant frequency and the total phase margin must be provided by the compensation network. however, with higher losses in the power stage (larger r s ) the q factor will be lower and the phase loss will occur more gradually. as a result, the power stage phase will not be as close to C180 at the crossover frequency and less phase boost is required of the compensation network. the ltc3112 error amplifier is designed to have a fixed maximum bandwidth in order to provide rejection of switching noise to prevent it from interfering with the control loop . from a frequency domain perspective, this can be viewed as an additional single pole as illustrated in figure 8. the nominal frequency of this pole is 400 khz. for typical loop crossover frequencies below about 60khz a pplica t ions i n f or m a t ion the phase contributed by this additional pole is negligible. however, for loops with higher crossover frequencies this additional phase loss should be taken into account when designing the compensation network. figure 8. internal loop filter. + ? 0.8v fb ltc3112 v comp r filt c filt 3112 f08 internal v comp loop compensation example this section provides an example illustrating the design of a compensation network for a typical ltc3112 applica - tion circuit. in this example a 5 v regulated output voltage is generated with the ability to supply a 1 a load from an input power source ranging from 3.5 v to 15 v. the nominal 750khz switching frequency has been chosen. in this ap - plication the maximum inductor current ripple will occur at the highest input voltage. an inductor value of 4.7h has been chosen to limit the worst case inductor current ripple to approximately 1 a. a low esr output capacitor with a value of 47 f is specified to yield a worst case output voltage ripple ( occurring at the worst case step-up ratio and maximum load current) of approximately 10 mv. in summary, the key power stage specifications for this ltc3112 example application are given below. f = 0.75mhz, t low = 0.2s v in = 3.5v to 15v v out = 5v at 1a c out = 47f, r c = 5m l = 4.7h, r l = 50m with the power stage parameters specified, the compen - sation network can be designed. in most applications, the most challenging compensation corner is boost mode operation at the greatest step-up ratio and highest load current since this generates the lowest frequency right half plane zero and results in the greatest phase loss. therefore, a reasonable approach is to design the compensation network at this worst case corner and ltc3112 3112fc for more information www.linear.com/ltc3112
22 then verify that sufficient phase margin exists across all other operating conditions. in this example application, at v in = 3.5 v and the full 1 a load current, the right half plane zero will be located at 60 khz and this will be a dominant factor in determining the bandwidth of the control loop. the first step in designing the compensation network is to determine the target crossover frequency for the com- pensated loop. a reasonable starting point is to assume that the compensation network will generate a peak phase boost of approximately 60. therefore, in order to obtain a phase margin of 60, the loop crossover frequency, f c , should be selected as the frequency at which the phase of the buck-boost converter reaches ?180. as a result, at the loop crossover frequency the total phase will be simply the 60 of phase provided by the error amplifier as shown below. phase margin = f buck-boost + f erroramplifier + 180 = C180 + 60 + 180 = 60 similarly, if a phase margin of 45 is required, the target crossover frequency should be picked as the frequency at which the buck-boost converter phase reaches ?195 so that the combined phase at the crossover frequency yields the desired 45 of phase margin. this example will be designed for a 60 phase margin to ensure adequate performance over parametric variations and varying operating conditions. as a result, the target crossover frequency, f c , will be the point at which the phase of the buck-boost converter reaches ?180. it is generally difficult to determine this frequency analytically given that it is significantly impacted by the q factor of the resonance in the power stage. as a result, it is best determined from a bode plot of the buck- boost converter as shown in figure 9. this bode plot is for the ltc3112 buck-boost converter using the previously specified power stage parameters and was generated from the small signal model equations using ltspice ? . in this case, the phase reaches ?180 at 35khz making f c = 35 khz the target crossover frequency for the compensated loop. from the bode plot of figure 9 the gain of the power stage at the target crossover frequency is 7 db. therefore, in order to make this frequency the crossover frequency in the compensated loop, the total loop gain at f c must be adjusted to 0db. to achieve this, the gain of the com- pensation network must be designed to be C7 db at the crossover frequency. at this point in the design process, there are three con - straints that have been established for the compensation network. it must have ?7 db gain at f c = 35 khz, a peak phase boost of 60 and the phase boost must be centered at f c = 35 khz. one way to design a compensation network to meet these targets is to simulate the compensated error amplifier bode plot in ltspice for the typical compensation network shown on the front page of this data sheet. then , the gain, pole frequencies and zero frequencies can be iteratively adjusted until the required constraints are met. alternatively, an analytical approach can be used to design a compensation network with the desired phase boost, center frequency and gain. in general, this procedure can be cumbersome due to the large number of degrees of freedom in a type iii compensation network. however the design process can be simplified by assuming that both compensation zeros occur at the same frequency, f z , and figure 9. converter bode plot, v in = 3.5v, i load = 1a frequency (hz) 10 gain (db) phase (deg) ?150 ?100 ?50 0 10k 1m 3112 f09 ?200 ?250 100 1k 100k 50 ?150 ?100 ?50 0 ?200 ?250 50 phase f c gain a pplica t ions i n f or m a t ion ltc3112 3112fc for more information www.linear.com/ltc3112
23 both higher order poles (f pole2 and f pole3 ) occur at the common frequency, f p . in most cases this is a reasonable assumption since the zeros are typically located between 1khz and 10 khz and the poles are typically located near each other at much higher frequencies. given this as - sumption, the maximum phase boost, f max , provided by the compensated error amplifier is determined simply by the amount of separation between the poles and zeros as shown by the following equation. f max = 4tan C1 f p f z ? ? ? ? ? ? C 270 a reasonable choice is to pick the frequency of the poles, f p , to be about 50 times higher than the frequency of the zeros, f z , which provides a peak phase boost of approxi- mately f max = 60 as was assumed previously. next, the phase boost must be centered so that the peak phase occurs at the target crossover frequency. the frequency of the maximum phase boost, f center , is the geometric mean of the pole and zero frequencies as shown below. f center = f p f z = 50 ? f z ? 7f z therefore, in order to center the phase boost given a factor of 50 separation between the pole and zero frequencies, the zeros should be located at one seventh of the cross - over frequency and the poles should be located at seven times the crossover frequency as given by the fol lowing equations. f z = 1 7 f c = 1 7 35khz ( ) = 5khz f p = 7f c = 7 35khz ( ) = 250khz this placement of the poles and zeros will yield a peak phase boost of 60 that is centered at the cross over frequency, f c . next, in order to produce the desired target crossover frequency, the gain of the compensation network at the point of maximum phase boost, g center , must be set to ?7db. the gain of the compensated error amplifier at the point of maximum phase gain is given by the following equation. g center = 10log 2 f p 2 f z ( ) 3 r top c fb ( ) 2 ? ? ? ? ? ? ? ? db assuming a multiple of 50 separation between the pole frequencies and zero frequencies this can be simplified to the following expression. g center = 20log 50 2 f c r top c fb ? ? ? ? ? ? db this equation completes the set of constraints needed to determine the compensation component values. specifi - cally, the two zeros, f zero1 and f zero2 , should be located near 5 khz. the two poles, f pole2 and f pole3 , should be located near 250 khz and the gain should be set to provide a gain at the crossover frequency of g center = C7db. the first step in defining the compensation component values is to pick a value for r top that provides an accept- ably low quiescent current through the resistor divider. a value of r top = 845 k? is a reasonable choice and is used in several applications circuits. next, the value of c fb can be found in order to set the error amplifier gain at the crossover frequency to ?7db as follows. g center = C7db = 20log 50 2 35khz ( ) 845k ? ( ) c fb ? ? ? ? ? ? c fb = 50 0.185 ? 10 12 ? antilog C7 20 ? ? ? ? ? ? ? 680pf the compensation poles can be set at 250 khz and the zeros at 5 khz by using the expressions for the pole and zero frequencies given in the previous section. setting the frequency of the first zero f zero1 , to 5 khz results in the following value for r fb . r fb = 1 2 680pf ( ) 5khz ( ) ? 45k ? a 33 k? was selected to split the two zeros slightly apart, giving a higher zero frequency of 7 khz. this leaves the free parameter, c pole , to set the frequency f pole1 to the common pole frequency of 250khz. a pplica t ions i n f or m a t ion ltc3112 3112fc for more information www.linear.com/ltc3112
24 c pole = 1 2 33k ? ( ) 250khz ( ) ? 22pf next, c ff can be chosen to set the second zero, f zero2 , to the common zero frequency of 5khz. c ff = 1 2 845k ? ( ) 5khz ( ) ? 40pf in this case c ff was selected at 47 pf giving a lower fre - quency of 4 khz for the second zero. finally, the resistor value r ff can be chosen to place the second pole. r ff = 1 2 47pf ( ) 250khz ( ) ? 13k ? a 10 k? is chosen giving a 325 khz pole frequency. now that the pole frequencies, zero frequencies and gain of the compensation network have been established, the next step is to generate a bode plot for the compensated error amplifier to confirm its gain and phase properties . a bode plot of the error amplifier with the designed compensation component values is shown in figure 10. the bode plot confirms that the peak phase occurs near 30 khz and the phase boost at that point is around 60. in addition, the gain at the peak phase frequency is C10 db, close to the design target. a pplica t ions i n f or m a t ion f c frequency (hz) 10 ?200 gain (db) phase (deg) 0 ?50 100 1k 10k 100k 3112 f10 1m ?100 ?150 50 100 ?200 ?150 0 ?50 ?100 50 100 gain phase figure 10. compensated error amplifier bode plot. the final step in the design process is to compute the bode plot for the entire loop using the designed compensation network and confirm its phase margin and crossover frequency. the complete loop bode plot for this example is shown in figure 11. the resulting loop crossover fre - quency is 25 khz and the phase margin is approximately 60. the crossover frequency is a bit lower than the design target of 35 khz, but farther away from the troublesome right half plane zero. frequency (hz) 10 ?60 gain (db) phase (deg) ?40 ?20 0 20 40 60 ?180 f c ?120 ?60 0 60 gain 120 180 100 1k 10k 100k 3112 f11 1m phase figure 11. complete loop bode plot. this feedback design example was done at 3.5v in , 5v out , and a 1 a load current. the phase margin in boost mode will decrease at lower v in s, higher v out s, load currents, or inductor values due to the right half plane zero shifting to a lower frequency. as a reminder, the amount of power stage q at the l-c resonant frequency is highly dependent on the r s term (series resistance) which includes the esr of the inductor and the ltc3112s low r on mosfets. lower total series resistances give a higher q, making the feedback design more difficult. higher series resistances lower the q, resulting in a lower loop cross over frequency. the bode plot for the complete loop should be checked over all operating conditions and for variations in component values to ensure that sufficient phase margin exists in all cases. the stability of the loop should also be confirmed via time domain simulation and by evaluating the transient response of the converter in the actual circuit. ltc3112 3112fc for more information www.linear.com/ltc3112
25 typical a pplica t ions 1,2 or 3 li-ion to 5v 0.1f 680pf v in 2.7v to 15v v out 2.2h 0.1f 33k 845k 158k 47pf 47f 1f 10k 42.2k 100pf to adc 1v per amp onoff sw1 bst1 v in v cc run gnd pwm/sync sw2 bst2 v out comp i out ovp fb ltc3112 v out 5v/2a v in > 5v 22f 3112 ta04 1.5mhz clock optional 22pf ltc3112 synchronized to 1.5mhz clock, 5v/2a output 3112 ta04a sw1 5v/div sw2 5v/div pwm/sync 5vdiv inductor current 1a/div 200ns/div 0.1f 680pf 22pf v in 3v to 12.6v 4.7h 0.1f 33k 845k 158k 47pf 47f 1f 10k 42.2k 100pf to adc 1v per amp onoff pwm burst sw1 bst1 v in v cc run gnd pwm/sync sw2 bst2 v out comp i out ovp fb ltc3112 v out 5v/1.5a v in > 4v 10f + ? 1-3 cell li-ion 3112 ta03 load current (a) 0.0001 efficiency (%) 100 70 80 50 60 90 30 40 0.01 10.1 3112 ta03a 0.001 pwm burst 3.6v in 7.2v in 10.8v in ltc3112 3112fc for more information www.linear.com/ltc3112
26 typical a pplica t ions 0.1f 680pf v in 15v to 2v v out 4.7h 0.1f 220f tant 22mf supercap 33k 845k 158k 47pf 47f 10k 42.2k 100pf to adc 1v per amp sw1 bst1 v in v cc run gnd pwm/sync sw2 bst2 v out comp i out ovp fb ltc3112 v out 5v/250ma 1f 3112 ta05 22pf 499k 1m 499k + 5v backup supply from supercap runs down to v in = 2v with 250ma load 3112 ta05a v in 5v/div v out 5v/div i load 500ma/div run 5v/div 500ms/div ltc3112 3112fc for more information www.linear.com/ltc3112
27 0.1f 680pf v in 4.7h 0.1f 33k 845k 158k 47pf 100f 10k 42.2k 100pf to adc 1v per amp 33pf 158k 1000k onoff sw1 bst1 v in v cc run gnd pwm/sync sw2 bst2 v out comp i out ovp fb ltc3112 v out 5v/2.5a, v in > 5v 100f 1f 3112 ta06 pwm burst 1050k 100pf ltc4352 ideal diode 12v adapter 1-or 2-series li-ion cells mbr735 22pf v out optional stepped response from 1 or 2 li-ion to 12v adapter source with v in feedforward network typical a pplica t ions 3112 ta06a v in 5v/div v out 2v/div input current 10a/div comp 500mvdiv 100s/div 3112 ta06b v in 5v/div v out 2v/div input current 1a/div comp 500mvdiv 1ms/div adapter plug-in adapter disconnect ltc3112 3112fc for more information www.linear.com/ltc3112
28 0.1f 820pf v in 4.5v to 15v 10h 0.1f 33k 2210k 158k 47pf 47f 1f 10k 42.2k 100pf to adc 1v per amp onoff pwm burst sw1 bst1 v in v cc run gnd pwm/sync sw2 bst2 v out comp i out ovp fb ltc3112 v out 12v 1a v in > 5v 2a v in > 9v 22f 3112 ta07 22pf regulated 12v output from wide input supply range typical a pplica t ions pwm 3112 ta07a load current (a) 0.0001 efficiency (%) 100 70 80 50 60 90 30 40 0.01 10.1 0.001 burst 5.0v in 12v in ltc3112 3112fc for more information www.linear.com/ltc3112
29 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjgd-2) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 2.44 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 4.34 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhd16) dfn rev a 1113 0.25 0.05 pin 1 notch 0.50 bsc 4.34 0.05 (2 sides) recommended solder pad pitch and dimensions 2.44 0.05 (2 sides) 3.10 0.05 0.50 bsc 0.70 0.05 4.50 0.05 package outline 0.25 0.05 dhd package 16-lead plastic dfn (5mm 4mm) (reference ltc dwg # 05-08-1707 rev a) ltc3112 3112fc for more information www.linear.com/ltc3112
30 p ackage descrip t ion fe20 (ca) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation ca please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc3112 3112fc for more information www.linear.com/ltc3112
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 06/13 clarified absolute maximum rating: i out voltage spec. clarified run threshold specification. clarified thermal considerations last paragraph. clarified ltc4352 part designator. clarified related parts list. 2 3 12 28 32 b 10/13 clarified buck mode small signal model text clarified c fb formula 18 23 c 06/14 clarified title of typical application clarified absolute maximum temperature range and ordering information clarified note 2, 3 temperature range on input operating range clarified graphs temperature range clarified maximum junction temperature 1 2 3, 4 6 12 ltc3112 3112fc for more information www.linear.com/ltc3112
32 ? linear technology corporation 2010 lt 0614 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3112 r ela t e d p ar t s part number description comments ltc3531 200ma buck-boost synchronous dc/dc converter v in = 1.8v to 5.5v, v out = 3.3v, i q = 16a, i sd < 1a , sot23, dfn package ltc3129 15v, 200ma synchronous buck-boost converter v in = 2.42v to 15v, v out = 1.4v to 15.75v, i q = 1.3a, i sd < 10na , qfn and msop packages ltc3533 2a (i out ), 2mhz synchronous buck-boost dc/dc converter v in = 1.8v to 5.5v, v out = 1.8v to 5.25v, i q = 40a, i sd < 1a , dfn package ltc3113 3a low noise synchronous buck-boost dc/dc converter v in or v out = 1.8v to 5.5v, i q = 40a, i sd < 1a, dfn and tssop packages ltc3534 7v, 500ma synchronous buck-boost dc/dc converter v in = 2.4v to 7v, v out = 1.8v to 7v, i q = 25a, i sd < 1a , dfn, gn package ltc3538 800ma synchronous buck-boost dc/dc converter v in = 2.4v to 5.5v, v out = 1.8v to 5.25v, i q = 35a, i sd < 5a , dfn package ltc3440 600ma (i out ), 2mhz synchronous buck-boost dc/dc converter v in = 2.5v to 5.5v, v out = 2.5v to 5.25v, i q = 25a, i sd < 1a , msop and dfn packages ltc3441 1.2a (i out ), 1mhz synchronous buck-boost dc/dc converter v in = 2.4v to 5.5v, v out = 2.4v to 5.25v, i q = 25a, i sd < 1a , dfn package ltc3442 1.2a (i out ), 2mhz synchronous buck-boost dc/dc converter with programmable burst mode operation v in = 2.4v to 5.5v, v out = 2.4v to 5.25v, i q = 35a, i sd < 1a , dfn package ltc3443 high current micropower 600khz synchronous buck-boost dc/dc converter v in = 2.4v to 5.5v, v out = 1.5v to 5.25v, i q = 28a, i sd < 1a , dfn package ltc3115-1 2a (i out ), 40v synchronous buck-boost dc/dc converter v in = 2.7v to 40v, v out = 2.7v to 40v, i q = 30a, i sd < 3a , dfn and tssop packages ltc3780 high efficiency, synchronous, 4-switch buck-boost converter v in = 4v to 36v, v out = 0.8v to 30v, i q = 1500a, i sd < 55a , qfn package ltc3785 10v, high efficiency, synchronous, no r sense ? buck-boost controller v in = 2.7v to 10v, v out = 2.7v to 10v, i q = 86a, i sd < 15a , qfn package ltc3101 wide v in , multi-output dc/dc converter and powerpath? controller v in = 1.8v to 5.5v, v out = 1.5v to 5.25v, i q = 38a, i sd < 15a , qfn package ltc3522 synchronous 400ma buck-boost and 200ma buck v in = 2.4v to 5.5v, v out = 2.2v to 5.25v, i q = 25a, i sd < 1a , qfn package ltc3530 wide input v oltage synchronous buck-boost dc/dc converter v in = 1.8v to 5.5v, v out = 1.8v to 5.25v, i q = 40a, i sd < 1a , dfn package typical a pplica t ion 0.1f 3300pf v in 5v to 15v 6.8h 0.1f 200k 2210k 158k 22f 68.1k 3300pf 68.1k v dac sw1 bst1 v in v cc run gnd pwmsync sw2 bst2 v out comp i out ovp fb ltc3112 v out 22f 1f 3112 ta07 47pf dac programs led current 1.0a at 0v, 500ma at 0.8v i out = (1-0.625 ? v dac )a open lamp at 12v vf = 3.6v per led at 1a 10w, 10v high intensity led driver with programmable current and low-loss sensing 3112 ta08a v in (v) 4 led current (ma) 1500 1000 1250 500 750 0 250 8 12 14 10 6 v dac = 0v v dac = 0.8v led current vs v in and dac voltage ltc3112 3112fc for more information www.linear.com/ltc3112

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